A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.