Design and Implementation of 12-bit Vedic Multiplier using Optimized Decoder-based Adder

A Multiplier is one of the arithmetic circuits which plays a major role in many computational systems-based real-time applications. The responsibility of power consumption in the system greatly depends on the power consumption of its multiplier. In this work, slice LUT’s, slices, IOB, delay, and power of the proposed 3x3 bit, 6x6 bit, and 12x12 bit novel decoder based Vedic multiplier using “Urdhva Tiryakbhayam” sutra are calculated and compared with the conventional multiplier. The simulation and synthesis of the proposed 3x3 bit, 6x6 bit, and 12x12 bit multiplier are performed using Artex-7 on Xilinx Vivado. The comparative study of the proposed Vedic multiplier with the existing Vedic multiplier exhibits a significant improvement in terms of resource utilization.