A novel approach to incorporate silica filler into no-flow underfill

No-flow underfill technology has been proven to have potential advantages over the conventional underfill technology. However, due to the interference of fillers with solder joint yield, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly using no-flow underfill, and has limited its application to large chip assemblies. This paper presents a novel approach to incorporate silica filler into no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is heavily filled with silica fillers. A design of experiment is implemented to investigate the effect of bottom layer thickness, viscosity and reflow profile on the solder wetting using quartz chip. FB250 daisy-chained test chips are assembled on FR-4 boards using this novel approach. A 100% yield of solder interconnect is achieved with filled no-flow underfill for the first time. Wetting of the eutectic SnPb solder to contact pad on the board is confirmed by SEM and optical microscopic observation.