Application Specific Testing for VLSI Benchmark Circuits

With the growing intricacy in digital circuits, the need for appropriate exhaustive methods for testing is on the rise due to the presence of various faults. These faults are needed to be addressed and test patterns found with minimum utilization of time. The proposed paper presents generation of test patterns for stuck-at faults and bridging faults, for both combinational and sequential benchmark circuits of ISCAS’85 and IS CAS’89, through Boolean satisfiability (SAT). The time taken for generating test patterns is compared with ATALANTA tool to show SAT based method produces the results in lesser time. The method uses the tools of MiniSat Solver and ATALANTA.