Coordinate Compression Strategy of Resistance and Reactance for MHz-Range Inverter System

This article proposes a coordinate impedance compression strategy for high frequency inverter systems. Based on a two parallel inverter structure, the strategy adopts two methodologies: 1) a passive
LC
network to adjust the current and voltage seen by each inverter module, and 2) an active modulation of the inverter input voltage and output voltage phase to adjust the load current distribution. For the proposed strategy, the resistance and reactance can be compressed coordinately, which can help the inverter to operate in high efficiency load range. The Half-Bridge Class D inverter is taken as an example to be analyzed. A 10-MHz prototype is built and the experimental results verify the correctness and feasibility of the proposed strategy.