Magnetically Coupled Single-Phase AC-AC Converter With Reduced Number of Passive Components

An AC-AC direct single-phase converter based on an impedance network is presented in this manuscript. It possesses all privileges of similar impedance source AC-AC converters such as buck-boost ability, maintaining or reversing the phase angle and sharing the same ground between input and output voltage. Furthermore, a magnetic coupling is exploited to provide high voltage gain by adjusting its turns ratio along with the duty cycle. A safe commutation strategy is implemented to avoid current and voltage spikes across switches needless to utilize snubber circuits. The presented converter offers continuous input current, and ac to ac conversion is done directly without using dc storage, making it appropriate for dynamic voltage restorer to compensate voltage sags and voltage swells. In addition, LC input and output filters are eliminated thanks to impedance network structure. In this regard, the presented topology offers good features in size and cost by reducing passive components compared to similar structures. Also, the comparative investigation shows that the proposed converter benefits from superior operational ranges among similar well-known topologies for the same conditions. Finally, theoretical analyses and operation modes of the proposed converter are discussed and testified by both simulation and experimental results.

SECTION I. Introduction

Over the recent years, single-phase dynamic voltage restorer (DVR) has been used widely to deal with power quality issues for sensitive loads. Single-phase AC-AC converters are exploited as effective series compensators in the DVR systems to compensate voltage sags and swells. The most used AC-AC converters applicable in voltage conditioners are indirect AC-AC converters, direct and indirect matrix converters, and direct PWM AC-AC converters. However, all these converters suffer from some drawbacks. Indirect AC-AC converters require costly battery banks and huge super-capacitors to supply dc sources [1]. Matrix converters utilize a high number of semiconductors devices with complex commutation and provide bounded voltage gain with a maximum of 0.86 [2], [3]. Direct PWM AC-AC converters provide slight current distortion, simple control, simple structure, small parameters, high efficiency, and improved power factor [4], [5]. However, most of them are not able to operate in buck-boost mode simultaneously and suffer from discontinuous input current.

To overcome the aforementioned drawbacks, traditional single-phase Z-source AC-AC converters were proposed in [6], [7]. Although they can both boost and buck input voltage, they suffer from discrete input current, unshared ground between input and output. Quasi Z-source AC-AC converter is introduced in [8] to solve unshared ground, discontinuous input current issues. Also, voltage stress across capacitors decreased dramatically compared to traditional single-phase Z-source AC-AC converters. In [9], a safe commutation strategy has been applied to a family of quasi Z-source AC-AC converters to remove voltage overshoots across switches without requiring snubber circuits, which causes conduction losses reduction along with efficiency improvement. To reduce the number of passive components, a modified quasi Z-source AC-AC converter is proposed in [10]. It provides high-quality output voltage without utilizing output LC filters.

Recently, magnetically coupled inductors have been used in various types of impedance source topologies. In dc-dc impedance source converters, coupled inductors are applied into impedance networks to provide high voltage boost ability with the small duty cycle of converters [11]. Meanwhile, coupled inductors based impedance source inverters appeal to researchers more and more because of their high voltage boost ability with high modulation ratio and low stress across the semiconductors devices [12]–​[19]. Single-phase Z-source AC-AC converters based on coupled inductors have been introduced to control ac voltage by adjusting their turn ratio besides the duty cycle of converters. In other words, coupled inductors give more options to impedance source AC-AC converters to regulate the ac output voltage. For instance, a transformer type of quasi Z-source AC-AC converter is presented in [20] to enhance voltage gain by increasing the turn ratio of the transformer along with the duty cycle changing. In order to reduce the size of the converter, an AC-AC impedance source converter based on $\Gamma$ structure is proposed to attain high voltage gain by reducing the turn ratio of coupled inductors [21]. However, it suffers from discontinuous input current with non-sinusoidal waveform and high THD. Therefore, input filter implementation is necessary to reduce harmonics of input current. Recently, a modified converter in [22] has been proposed to solve the discontinuous input current problem of the topology in [21]. An inductor-less filter has been implemented in an improved single-phase trans-Z-source AC-AC converter in [23], which offers unique features such as improved power density, restrained low-frequency oscillation, and less phase shift between the input and output voltage. Nonetheless, it must employ two more IGBT switches than other single-phase impedance source AC-AC counterparts. A class of transformer-based single-phase Z-source AC-AC converters have been presented in [24] with the combination of two coupled inductors which provide wide range of voltage gain by either increasing or decreasing the turns ratio of coupled inductors. Although, employing two transformers raises the cost and size of the converter. A family of high-frequency transformer isolated (HFTI) based Z-source AC-AC converters have been proposed in [25], [26] to be utilized as DVR without using bulk, expensive and heavy line frequency transformers. These converters employ extra passive components and additional bidirectional switches, which increase their losses, size, and cost. A modified single-phase $\Gamma$ -source AC-AC converter has been presented in [27], which employs fewer number of components with a reduced number of transformer’s turn ratio. However, high distortion is produced for high output voltage when the transformer’s turn ratio approaches 1.

In this paper, a single-phase AC-AC converter based on coupled inductors is presented. The proposed converter has a lower number of passive components compared to similar counterparts. Its impedance source network structure produces high voltage gain with high-quality waveforms without input and output LC filter. Also, coupled inductors help the converter to attain desired voltage gain with small conducting pulses in a safe commutation strategy. Consequently, the proposed converter offers the turn ratio of coupled inductors as an extra control variable along with the converter’s duty cycle. Also, output voltage shares the same ground with input which can reverse and maintain phase angle well. Circuit analysis and operation theory are detailed in the rest of the paper, and experimental tests are performed on a laboratory prototype to verify the theoretical results. In addition, a dynamic voltage restorer based on the proposed converter is presented to compensate voltage sag and voltage swell. Simulation results are provided to show the ability of the proposed converter in voltage sag and swell compensation. Furthermore, the power loss analysis of the proposed converter is then presented and finally, the conclusion of the paper is included.

SECTION II. Proposed Magnetic Coupled Single-Phase AC-AC Converter

A. Circuit Description

The overview of the proposed AC-AC converter is shown in Fig. 1. The presented structure consists of ac input voltage, impedance network, and resistive load. Two bidirectional switches have been embedded in the impedance network. Impedance network includes input inductor (L), two capacitors (C₁ and C₂), two bidirectional switches ($\text{S}_{\mathrm {1i-j}}$ ,$\text{S}_{\mathrm {2i-j}}$ ), one coupled inductor with two windings ($\text{N}_{\mathrm {p}}$ , $\text{N}_{\mathrm {s}}$ ) where N=Ns/$\text{N}_{\mathrm {P}}$ represents its turns ratio. It must be noted that each bidirectional switches consist of two back to back separated switches. It is clear that the proposed topology utilizes passive components of impedance network instead of input and output filters to reduce switching ripple and harmonic components found in input and output sides. Hence, it saves two inductors and two capacitors in input and output, resulting in lower cost and smaller size of the converter. Furthermore, utilized coupled inductor provides high voltage gain by adjusting turns ratio of the high-frequency transformer. Input inductor connects in series to the input ac source makes the current continuous that brings advantages such as reduced in-rush current, low harmonic, better power factor, and improved efficiency. Also, input and output sides share the same ground, so the converter can operate in both boost in-phase mode and buck-boost out of phase mode, and output can reverse or maintain phase angle with input well.

FIGURE 1.

Proposed magnetically coupled AC-AC converter.

B. Operation Principle

Due to dead time and overlap of switches and their speed limitation practically, inductors currents and capacitors voltages might be changed instantly and produce voltage and current spikes across the power switches, which can destroy them. As a result, a snubber circuit must be implemented to provide voltage and current laws of Kirchhoff and to prevent these destructive spikes. However, snubber circuits increase the cost and complexity of the converter and decrease its efficiency. Hence, a safe commutation strategy has been applied to the proposed converter to prevent voltage and current spikes.

Fig. 2 demonstrates the switching pattern of safe commutation strategy for the proposed converter in “boost/buck” “in phase/out of phase” modes. Accordingly, by considering the dead time situation in ideal switches, the switching pattern is formed by input voltage’s polarity:

• $\text{V}_{\mathrm {i}}$ is positive, and converter operates in “in-phase” mode, $\text{S}_{\mathrm {1i}}$ is fully turned on to provide the current path, and $\text{S}_{\mathrm {2j}}$ is turned on for dead time issue.

• $\text{V}_{\mathrm {i}}$ is positive, and the converter performs in “in-phase” mode, $\text{S}_{\mathrm {2i}}$ and $\text{S}_{\mathrm {2j}}$ are turned on to provide the current path, and $\text{S}_{\mathrm {1i}}$ is fully turned on to prevent the commutation problem throughout the dead time duration.

• $\text{V}_{\mathrm {i}}$ is negative, and converter operates in “in-phase” mode, $\text{S}_{\mathrm {1j}}$ is conducting as the current path, and $\text{S}_{\mathrm {2i}}$ is turned on because of dead time condition.

• $\text{V}_{\mathrm {i}}$ is negative, and converter performs in “in-phase” mode, $\text{S}_{\mathrm {2i}}$ and $\text{S}_{\mathrm {2j}}$ is turned on to provide the current path and $\text{S}_{\mathrm {1j}}$ is fully turned on for dead time situation.

• $\text{V}_{\mathrm {i}}$ is positive, and converter operates in “out-of-phase” mode, $\text{S}_{\mathrm {1i}}$ and $\text{S}_{\mathrm {1j}}$ are switched on to provide the current path and $\text{S}_{\mathrm {2i}}$ is turned on to prevent the commutation problem throughout the dead time.

• $\text{V}_{\mathrm {i}}$ is positive, and converter performs in “out-of-phase” mode. $\text{S}_{\mathrm {2i}}$ and $\text{S}_{\mathrm {2j}}$ are switched on as the current path and $\text{S}_{\mathrm {1j}}$ is turned on to prevent the commutation problem throughout the dead time.

• $\text{V}_{\mathrm {i}}$ is negative, and converter operates in “out-of-phase” mode, $\text{S}_{\mathrm {1i}}~\text{S}_{\mathrm {1j}}$ are conducting as the current path and $\text{S}_{\mathrm {2j}}$ is switched on due to the dead time condition.

• $\text{V}_{\mathrm {i}}$ is negative, and converter operates in “out-of-phase” mode, $\text{S}_{\mathrm {2i}}$ and $\text{S}_{\mathrm {2j}}$ are switched on as the current path and $\text{S}_{\mathrm {1i}}$ is switched on to prevent commutation problem.

FIGURE 2.

Switching pattern of safe commutation strategy for boost/buck (a) in-phase mode, and (b) out-of-phase mode.

Fig. 3 illustrates the switching signals and key waveforms of the presented converter when it operates in “in-phase” mode when input voltage is positive. It can be seen that $\text{S}_{\mathrm {1i}}$ and $\text{S}_{\mathrm {2j}}$ are fully turned on, and $\text{S}_{\mathrm {2i}}$ is switching at high frequency. Various current paths of the proposed converter in the boost in-phase mode have been illustrated in Fig. 4 and Fig. 5. Fig. 4 shows operation states of the proposed converter when the input voltage is positive, including state I, dead times intervals, and state II. Fig. 4 (a) depicts state I that switch $\text{S}_{\mathrm {1i}}$ is switched on to provide positive current from ac source to load, and S2j is switched on to eliminate commutation problem in a dead time interval, and $\text{S}_{\mathrm {2i}}$ is remained switched off. It must be noted that S1j can be either switched on or switched off. In similar kinds of literature, S1j- S2i (when Vi>0) and S1i- S2j (when Vi<0) are considered complementary switches, while in this paper, similar to [21], switch S1j is entirely turned off when Vi > 0 and switch $\text{S}_{\mathrm {1i}}$ is completely switched off when Vi < 0 due to two reasons: (1). Every switching on and off of the S1i and S1j consist of switching losses. Hence this strategy increases the lifetime of switches. (2). According to Fig. 2 in boost in-phase mode, voltage boost ability depends on the pulse width of $\text{S}_{\mathrm {2i}}$ and $\text{S}_{\mathrm {2j}}$ that is defined as (1-d) T where d and T are defined as duty cycle and switching period of the converter, respectively. As a result, employed coupled inductor helps the proposed converter to obtain high voltage boost ability by decreasing the conducting pulse width of switches. So, in this case, lower (1-d) and higher d are desired. At the same time, this opportunity cannot be attained by complementary modes since decreasing conducting pulse width of $\text{S}_{\mathrm {2i}}$ leads to an increment in conducting pulse width of $\text{S}_{\mathrm {2i}}$ . The same situation will happen for S1i and S2j. To provide state II, three various situations can occur before turning on the $\text{S}_{\mathrm {2i}}$ and during dead time. From Fig. 4 (b) if $I_{i}+I_{Lk} >0$ , $\text{S}_{\mathrm {1i}}$ will conduct the current flow. If $I_{i}+I_{Lk} < 0$ , two situations may happen; for $I_{Lk}=I_{Lm}$ , $\text{S}_{\mathrm {2j}}$ conducts current flow as shown in Fig. 4 (c), but for $I_{Lk} < I_{Lm}$ , current must flow through $\text{S}_{\mathrm {1i}}$ to energy stored in Lm decrease. As shown in Fig. 4 (d), this situation will continue until the stored energy of $L_{m}$ and $L_{k}$ becomes balanced where $\text{L}_{\mathrm {k}}$ and $L_{m}$ represent leakage inductance and magnetizing inductance, respectively. Finally, state II will occur by switching on $\text{S}_{\mathrm {2i}}$ -$\text{S}_{\mathrm {2j}}$ , and $\text{S}_{\mathrm {1i}}$ is turned on to prevent commutation problems, which is demonstrated in Fig. 4 (e).

FIGURE 3.

Key waveforms of the proposed converter’s components in boost in-phase mode when Vi > 0.

FIGURE 4.

Operation intervals of the proposed converter in boost in-phase mode when Vi > 0, (a): state I, (b): commutation mode when $\text{I}_{\mathrm {i}}+\text{I}_{\mathrm {Lk}}>0$ , (c): commutation mode when $\text{I}_{\mathrm {i}}+\text{I}_{\mathrm {Lk}} <$ 0 and $\text{I}_{\mathrm {Lk}}=\,\,\text{I}_{\mathrm {Lm}}$ , (d): commutation mode when $\text{I}_{\mathrm {i}}+\text{I}_{\mathrm {Lk}}<$ 0 and $\text{I}_{\mathrm {Lk}}$ -$\text{I}_{\mathrm {Lm}}< 0$ , (e): state II.

FIGURE 5.

Operation intervals of the proposed converter in buck out-of-phase mode when Vi > 0, (a): state I, (b): commutation mode when $\text{I}_{\mathrm {i}}+\text{I}_{\mathrm {Lk}}< 0$ , (c): commutation mode when $\text{I}_{\mathrm {i}}+\text{I}_{\mathrm {Lk}} >$ 0 and $\text{I}_{\mathrm {Lk}}=\,\,\text{I}_{\mathrm {Lm}}$ , (d): commutation mode when $\text{I}_{\mathrm {i}}+\text{I}_{\mathrm {Lk}} >$ 0 and $\text{I}_{\mathrm {Lk}}$ - $\text{I}_{\mathrm {Lm}} >0$ , (e): state II.

Fig. 5 illustrates operating intervals of the proposed converter in buck out-of-phase mode when the input voltage and the output voltage are positive and negative, respectively. Fig. 5 (a) depicts state I when switch $\text{S}_{\mathrm {1j}}$ is turned on to provide the current path and $\text{S}_{\mathrm {2i}}$ is turned on due to solving the commutation problems. In order to prepare state II, three different situations may occur before turning on the $\text{S}_{\mathrm {2j}}$ during dead time. From Fig. 5 (b), if $I_{i}+I_{Lk} < 0$ , $\text{S}_{\mathrm {1j}}$ will flow the current. If $I_{i}+I_{Lk} >0$ , two conditions could occur according to the stored energy of $L_{k}$ and $L_{m}$ . If $I_{Lk}= I_{Lm}$ , the current will be conducted through $\text{S}_{\mathrm {2i}}$ , which can be seen in Fig. 5 (c). But there is a situation when stored energy in Lk is lower than that in Lm. In this case, S1j must be switched on until the stored energy of Lm and Lk become equal. This condition can be observed in Fig. 5 (d). Lastly, state II will happen by turning on $\text{S}_{\mathrm {2i}}$ -$\text{S}_{\mathrm {2j}}$ , and $\text{S}_{\mathrm {1j}}$ is turned on to avoid commutation problem, which is illustrated in Fig. 5 (e).

C. Circuit Analysis

Following assumptions have been considered for the proposed circuit analysis: (1) It operates in continuous conduction mode (CCM). (2) The parasitic resistance of input inductor ($\text{r}_{\mathrm {L}}$ ), coupled inductors ($\text{r}_{\mathrm {Lm}}$ ) and switches ($\text{r}_{\mathrm {S}}$ ) are considered. (3) The equivalent series resistance (ESR) of capacitors ($\text{r}_{\mathrm {C}}$ ) are equal. (4) Frequency of the input and output voltages are lower than the switching frequency. (5) The coupling sufficient ($K$ ) is defined as $\frac {L_{m}}{L_{m}+L_{K}}$ and the turn ratio of coupled inductors ($N$ ) equals$\frac {v_{N_{S}}}{v_{N_{P}}}=\frac {I_{N_{P}}}{I_{N_{S}}}$ . (6) The dead time effects of switches are ignored. Hence, the proposed converter operates in two states in each switching period, which are visualized in Fig. 6. Fig. 6 (a) illustrates the equivalent circuit of state I with the time interval of dT that S₁ is conducting and S₂ is turned off. In this state, the input and coupled-inductors are charged by C₂ and C₁. By applying KVL and KCL, equation (1), as shown at the bottom of the next page,

can be derived.

FIGURE 6.

Equivalent circuits of the proposed converter in one switching period, (a). dT interval (state I), (b). (1-d) T interval (state II).

Also, Fig. 6 (b) shows the equivalent circuit of state II with the time interval of (1-d)T. In this mode, S₂ is conducting while S₁ turns off. The stored energy in the input and coupled-inductors are released to the capacitors as in equation (2), as shown at the bottom of the next page.

According to (1) and (2), the average equations in one switching period are obtained as:

In the steady-state, the average value of the voltage/current across the inductor and coupled inductors/capacitors is zero, so by considering zero for equations (3), as shown at the bottom of the next page,

the peak of $\text{I}_{\mathrm {i}}$ , the peak of $I_{Lm}$ , the peak of $v_{C_{1}}$ and the peak value of $v_{O}$ can be derived. In the ideal case resistance of inductors, capacitors, and power switches are negligible. Hence, to avoid complex equations, it is assumed that $\text{r}_{\mathrm {Lm}}= \text{r}_{\mathrm {L}}= \text{r}_{\mathrm {C}} = \text{r}_{\mathrm {S}}=0$ . Thus, it yields: $$\begin{align*} \begin{cases} \\ I_{i}=\frac {d}{N\left ({d-1 }\right)+2d-1}\frac {v_{o}}{R} \\[0.5pt] I_{L_{m}}=\frac {N\left ({d-1 }\right)+d-1}{N\left ({d-1 }\right)+2d-1}\frac {v_{o}}{R} \\[0.5pt] v_{C1}=\frac {NK\left ({1-d }\right)+1-d}{NK\left ({d-1 }\right)+2d-1}v_{i} \\[0.5pt] v_{o}=\frac {d}{NK\left ({d-1 }\right)+2d-1}v_{i} \\ \\ \end{cases}\tag{4}\end{align*}$$ Considering K=1, the voltage gain can be obtained as: $$\begin{equation*} G_{v}=\frac {v_{o}}{v_{i}}=\frac {d}{N\left ({d-1 }\right)+2d-1}\tag{5}\end{equation*}$$ The $L_{m}$ current gain can be defined as: $$\begin{equation*} G_{I}=\frac {I_{L_{m}}}{I_{i}}=\frac {N\left ({d-1 }\right)+d-1}{d}\tag{6}\end{equation*}$$

Fig. 7 illustrates output voltage gain versus duty cycle with the various turn ratios of coupled inductors. Clearly, the proposed converter follows a different characteristic curve compared to previous single-phase AC-AC impedance source converters. It can be seen that in boost in-phase mode, the proposed converter provides higher voltage gain with lower conducting pulse width by increasing transformer’s turn ratio. Furthermore, there are two operation regions based on the duty cycle range. For $d>\frac {N+1}{N+2}$ , the proposed converter operates in boost in-phase mode, and when $d< \frac {N+1}{N+2}$ , the proposed converter operates in buck/boost out-of-phase mode.

FIGURE 7.

Relationship between voltage gain and duty cycle of the introduced converter with various N.

SECTION III. Circuit Design of the Proposed Converter

Initially, the magnetic components of the proposed converter should be designed. Accordingly, the inductors parameters of the proposed converter are determined according to their maximum voltage and current ripple in dT interval. Regarding Fig. 5 (a), in the state I, the maximum voltage of L and $L_{m}$ are $V_{i}-V_{C2}$ and $\frac {V_{C1}}{N+1}$ , respectively. So we can get:

$$\begin{align*} \begin{cases} \\ L=\frac {\left |{ V_{imax}-V_{C2max} }\right |dT}{\Delta I_{i}} \\ Lm=\frac {\left |{ \frac {V_{C1}max}{N+1} }\right |dT}{\Delta I_{L_{m}}} \\ \\ \end{cases}\tag{7}\end{align*}$$ If $\Delta \mathrm {I}_{\mathrm {i}}$ and $\mathrm {\Delta }\mathrm {I}_{\mathrm {L}_{\mathrm {m}}}$ are determined as $\mathrm {\Delta }\mathrm {I}_{\mathrm {i}}\le x\% i_{i}$ and $\Delta I_{L_{m}}\le x\% i_{L_{m}}$ , respectively, equation (8), as shown at the bottom of the page,

can be obtained.

Where $i_{i}$ and $i_{L_{m}}$ represent RMS values of L and Lm current, respectively. In addition, the capacitors’ parameters of the proposed converter are determined based on their maximum current and voltage ripple in dT interval. From Fig. 5 (a) in the state I, the maximum current of C₁ and C₂ are ($\frac {-1}{N+1}I_{L_{m}}$ ) and (Ii-Io), respectively. So (9) can be R

$$\begin{align*} \begin{cases} \\ C_{1}=\frac {\left |{ \frac {1}{N+1}I_{L_{m}} }\right |dT}{\Delta v_{C1}} \\ C_{2}=\frac {\left |{ \mathrm {Ii-Io} }\right |dT}{\Delta v_{C2}} \\ \\ \end{cases}\tag{9}\end{align*}$$

If $\Delta \mathrm {v}_{\mathrm {C1}}$ and $\mathrm {\Delta }\mathrm {v}_{\mathrm {C2}}$ are determined as $\Delta v_{C1}\le y\% V_{C1}$ and $\Delta v_{C2}\le y\% V_{C2}$ , respectively, we can obtain, equation (10), as shown at the bottom of the page.

Where, $V_{C1}$ and $V_{C2}$ represent RMS values of C₁ and C₂ voltage, respectively. Noteworthy, the maximum value of voltage stress of bidirectional switches can be obtained from (4) and (5) as follows:

$$\begin{align*} \begin{cases} \\ V_{S1,max}=\frac {\sqrt {2} (N+1)}{N\left ({d-1 }\right)+2d-1}v_{i} \\ V_{S2,max}=\frac {\sqrt {2}}{N\left ({d-1 }\right)+2d-1}v_{i} \\ \\ \end{cases}\tag{11}\end{align*}$$

The peak and RMS current stress of the bidirectional switches can be obtained as (12) and (13), respectively.

$$\begin{align*} \begin{cases} \\ I_{S1,max}=\frac {\sqrt {2}~P_{O}}{dv_{i}} \\ I_{S2,max}=\frac {\sqrt {2} (N+1)P_{O}}{dv_{i}} \\ \\ \end{cases} \tag{12}\\ \begin{cases} \\ I_{S1,rms}=\frac {\left ({\sqrt {1-d} }\right)P_{O}}{dv_{i}} \\ I_{S2,rms}=\frac {\sqrt {d} (N+1)P_{O}}{dv_{i}} \\ \\ \end{cases}\tag{13}\end{align*}$$

SECTION IV. Application of the Proposed Converter as Dynamic Voltage Restorer

Fig. 8 depicts a dynamic voltage restorer based on the proposed single-phase ac-ac converter. The line voltage Vi is linked to the input of the proposed converter in shunt. Also, the output of the converter is connected in series with the line voltage and load by an injection transformer. Since the injection transformer ratio is 1:1, the compensation voltage $V$ com is equal to the converter output voltage $V_{C2}$ . In the other words, the proposed DVR adjusts the load voltage Vo by injecting in-phase/out-of-phase boost/buck voltage in series with the line voltage in three operation states as follows:

FIGURE 8.

Proposed dynamic voltage restorer.

A. Bypass Mode

In this mode, the line voltage has the normal amount without voltage sag/swell faults. In this state, the proposed converter operates with the duty cycle of 1 and the output voltage of 0, when the bidirectional switch S₁ is entirely switched off, while the bidirectional switch S₂ conducts fully.

B. Boost In-Phase Mode

This state starts when the voltage sag happens and the line voltage is lower than the determined amount. In this mode the proposed topology performs in boost in-phase state. From (5) and Fig. 8, by applying KVL we can get

$$\begin{equation*} v_{o}=v_{i}+v_{com}=v_{i}+\left({\frac {d}{N\left ({d-1 }\right)+2d-1}}\right)v_{i}\tag{14}\end{equation*}$$

C. Buck Out-of-Phase Mode

This mode starts when the voltage swell occurs and the line voltage is higher than the determined value. In this state the proposed converter operates in buck out—of-phase mode. Again from (5) and Fig. 8, by applying KVL we can obtain

$$\begin{equation*} v_{o}=v_{i}-v_{com}=v_{i}-\left({\frac {d}{N\left ({1-d }\right)-2d+1}}\right)v_{i}\tag{15}\end{equation*}$$

By assuming N=2, the load voltage can be obtained as:

$$\begin{equation*} v_{o}=\left({\frac {5d-3}{4d-3}}\right)v_{i}\tag{16}\end{equation*}$$

From (16), the load voltage gain versus the switching duty ratio is shown in Fig. 9. According to Fig. 9, the presented DVR can compensate up to over 50% voltage sag for D = (0.75, 1). Additionally, the proposed DVR can compensate voltage swell when D = [0, 0.6).

FIGURE 9.

Load voltage gain versus duty cycle in voltage sag and swell condition.

SECTION V. Comparative Study

Since the voltage characteristic of the proposed converter is different from other topologies, its voltage gain is compared to that in modified quasi Z-source single-phase AC-AC converters, which offer the same voltage characteristic curve. Fig. 10 shows that the proposed converter provides higher voltage gain with a lower conducting pulse width (higher d and lower 1-d) than the modified single-phase quasi Z-source AC-AC converter in the boost mode. Compared to the asymmetrical $\Gamma$ -source AC-AC converter, the proposed topology provides a wider range for the transformer turns ratio to increase voltage gain for the boost in-phase mode.

FIGURE 10.

Relationship between voltage gain and duty cycle of the modified single-phase qZS AC-AC converter and introduced converter with various N.

The proposed converter exploited a different structure of the windings compared with the converter in [27]. This diversity brings some advantages to the proposed converter. In [27], the voltage gain can be increased by lowering the transformer’s turn ratio. However, it can be a plus, especially in terms of the size; the converter suffers from the narrow range of the turn ratio. In other words, the practical range of the turn ratio for the high voltage requirement is 1.5 to 1.3, which can be a limitation for the design issue. Because by lowering the turn number in practice, distortion in output waveforms will occur. To solve this problem, the proposed converter attains high voltage boost/buck ability by increasing the turns from 1 to more than 6 in the design process according to the required voltage compensating in voltage sag/swell problems. Unlike conventional z-source and $\Gamma$ -source AC-AC converters, the presented structure offers a continuous sinusoidal input current with lower THD.

In addition, the proposed converter exploits a reduced number of passive components compared to topologies in [20]–​[24]. Likewise, the proposed converter utilizes a lower number of active components in comparison to the modified trans-Z-source AC-AC converter [23]. In this regard, a detailed comparison between the proposed topology and similar single-phase direct AC-AC converters is provided in Table 1 to 4. This investigation encompasses the operational, structural, and performance considerations of the proposed single-phase direct AC-AC converter as well as other similar ones. Accordingly, the number of active and passive components including inductors ($\text{N}_{\mathrm {I}}$ ), coupled inductors ($\text{N}_{\mathrm {CI}}$ ), power switches ($\text{N}_{\mathrm {SW}}$ ), the total number of circuit components ($\text{N}_{\mathrm {total}}$ ) are considered. Furthermore, voltage gain, voltage/current equations of capacitors/inductors, input current, voltage and current stress of the semiconductors are taken into account. Finally, a brief comparison of the pros and cons of each circuit design is presented in Table 4.

TABLE 1 Operational Parameter Design Considerations of the Proposed Topology Versus Similar Single-Phase AC-AC Converters

TABLE 2 Structural Parameter Designs of the Proposed Topology and Similar Single-Phase AC-AC Converters

TABLE 3 Performance Criteria of the Proposed Topology and Similar Single-Phase AC-AC Converters

TABLE 4 Overall Investigation of the Proposed Topology Compared to Similar Single-Phase AC-AC Converters

SECTION VI. Evaluation and Results

To further investigate the correctness of the proposed topology, the circuit configuration was simulated in MATLAB environment. Then, the simulation results were compared to experimental ones obtained from a laboratory prototype presented in Fig.11. The setup specification is brought in table 5. Particularly, the safe-commutation strategy is performed by utilizing the digital signal processor (DSP-TMS320F28335). Two bidirectional switches have been used to implement the safe commutation strategy. Notably, each bidirectional switch consists of two back to back Power MOSFETs. High frequency coupled inductors have been designed with the turns number of ten and twenty for the primary and secondary sides, respectively. Also, each circuit component is chosen for the circuit design and its mathematical analyses described in previous sections. In addition, both of the simulations and experimentations were conducted in the same conditions. Accordingly, the experimental results of the proposed converter supplying a resistive load ($80\Omega$ ) in boost in-phase operating mode are presented in Fig.12.

TABLE 5 Topology Properties

FIGURE 11.

Picture of the implemented setup.

FIGURE 12.

Boost operating mode behavior of the proposed converter includes: (a) input waveforms, (b) output waveforms, (c) input vs output, (d) S₁, and (e) S₂.

In this state, the duty cycle is assumed 0.9. The input voltage waveform is depicted in Fig.12.a. According to Table 5 and the obtained mathematical equations, the peak value of the output voltage, input current, and output current are approximately 150 V, 2.8 A, and 1.8 A, respectively verified by experimental waveforms in Fig. 12.a-c. This case (boost factor of 1.5) can be a suitable range for the 50% voltage sag compensation, applicable in dynamic voltage restorer. To achieve this boost factor by the modified single-phase AC-AC quasi Z-source converter, the duty cycle must be considered as d = 0.75. In other words, the pulse width of the $\text{S}_{\mathrm {2i}}$ and $\text{S}_{\mathrm {2j}}$ is 25% of the switching period. While with the same condition, the switches pulse width is 10% of the switching period in the proposed converter. Hence, the introduced topology can attain the equal voltage boost factor by the slighter conducting losses that increase the efficiency. Furthermore, the overview of the boost mode operation of the proposed converter can be seen in Fig.12.c describing the output voltage maintains the phase angle with the input voltage well. Additionally, the current and voltage waveforms of the switches in such operating conditions are added to Fig.12.d and e. From these figures, it can be seen that the voltage and current spikes across the switches have been eliminated thanks to the safe commutation strategy.

On the other hand, the operation of the proposed converter supplying a purely resistive load ($10\Omega$ ) in buck out-of-phase operating mode is investigated and the results are presented in Fig.13. In this state, the duty cycle is considered as d=0.2. The noticeable point for these waveforms is their phase differences. Unlike input and output voltage phase alignment in boost mode, there is 180 degrees phase deviation in buck operating mode. From theoretical equations, the peak value of the output voltage, input current, and output current are about 9 V, 0.1 A, and 1 A, respectively, which are verified by experimental results in Fig. 13.a to c. This case (boost factor of 0.09) can be appropriate for the range of the 10% voltage swell compensation. In addition, low peak value of the output voltage shows the high voltage buck ability of the proposed converter. From the experimental results, it is obvious that the input current is continuous and sinusoidal, completely in both boost and buck operating modes.

FIGURE 13.

Buck mode results of the proposed converter include: (a) input and output voltage waveform, (b) input waveforms, and (c) output waveforms.

The output voltage and input current THD of the proposed converter in boost and buck operation modes are presented in Table 6. It is clear that in buck operation mode, the output voltage and input current THDs are about 2.67% and 45.85%. Also, in boost operation mode, the output voltage and input current THDs are about 2.37% and 3.20%. As a result, the proposed converter offers high-quality voltage and current waveforms without utilizing input and output filters. In addition, Table 7 compares the input current THD of the proposed topology versus the similar converters. From this table, it can be found that in the boost mode, the presented topology has a lower input current THD than the other converters, while providing it in the reasonable value in the buck mode.

TABLE 6 Harmonic Contents of the Proposed Converter

TABLE 7 Input Current THD of the Proposed Converter Versus Similar Ones

Fig. 14 shows the simulation waveforms of the proposed converter with non-linear load for input frequency of 60 Hz, RMS input voltage of 73 V, duty cycle of 0.9, and transformer turn ratio of 2. A single-phase diode bridge rectifier with output capacitor of 470 $\mu \text{F}$ has been determined for a non-linear load [28], [29]. Fig. 14(a) and Fig. 14(b) show the input and output voltage waveforms, respectively. It can be seen that the proposed converter provides a sinusoidal output voltage under non-linear load. Furthermore, it is shown that the output voltage maintains the phase angle with the input voltage well. Fig. 14(c) shows the input current waveform. The THD of the input current and output voltage is about 27% and 12%, respectively.

FIGURE 14.

Simulation waveforms of the proposed converter with non-linear load: (a) input and (b) output voltages, (c) input current.

Fig. 15 and Fig. 16 show the simulation results of the voltage sag and voltage swell compensation by utilizing the DVR based on the proposed converter. A proportional integral (PI) controller has been used to control the load voltage. According to Fig. 15, when 60% voltage sag occurs in line voltage at interval time of 0.2–0.3 sec, the load voltage is well compensated to a demanded value of 110 $\text{V}_{\mathrm {rms}}$ . From Fig. 16, when 60% voltage sag happens in the line voltage at interval time of 0.2–0.3 sec, the load voltage is adjusted by the proposed DVR with a demanded value of 110 $\text{V}_{\mathrm {rms}}$ .

FIGURE 15.

Simulation waveforms of the proposed DVR at 60% voltage sag compensation: (a) line voltage, (b) compensation voltage, (c) load voltage.

FIGURE 16.

Simulation waveforms of the proposed DVR at 60% voltage swell compensation: (a) line voltage, (b) compensation voltage, (c) load voltage.

SECTION VII. Power Loss Analysis

The main power losses of the proposed converter come from the magnetic losses, semiconductors losses, and ESR of the capacitors. The magnetic losses include copper and core losses. Based on [30], the copper losses of the inductor and coupled inductors can be calculated from (17) and (18), respectively.

$$\begin{align*} P_{cu-L}=&\frac {\rho \left ({MLT }\right)I_{i}^{2}}{W_{A}K_{u}} \tag{17}\\ P_{cu-CI}=&\frac {\rho \left ({MLT }\right)n_{1}^{2}{(I_{Np}+{NI}_{Ns})}^{2}}{W_{A}K_{u}}\tag{18}\end{align*}$$ where $\rho$ , $MLT$ , $n_{1}$ , $I_{i}$ , $I_{Np-S}$ , $W_{A}$ , $K_{u}$ present the wire effective resistivity, mean length per turns, primary winding turns, RMS current of inductor, RMS current of winding, core window area, and winding fill factor, respectively. Also, the core loss is obtained from (19). Notably, $K_{fe}$ , $B_{max}$ , $\beta$ , $A_{C}$ , $l_{m}$ represent core loss coefficient, peak ac flux density, core loss exponent, core cross-sectional area, and mean magnetic path length, respectively. $$\begin{equation*} P_{fe}=K_{fe}B_{max}^{\beta }A_{c}l_{m}\tag{19}\end{equation*}$$ Hence, the total magnetic loss can be obtained from (20). $$\begin{equation*} P_{M-tot}=P_{cu-L}+P_{cu-CI}+P_{fe}\tag{20}\end{equation*}$$

Moreover, semiconductor loss itself comprises switching and conduction loss, whereas the former is originated from the time delay in turning ON or OFF of the device and the latter is caused due to the parasitic resistance of the device [31]. Also, switching loss is caused by an inherent behavior of all switching devices that can be calculated by:

$$\begin{align*} P_{s,on}=&\frac {1}{6}f_{s} V_{off-state} I_{on-state} t_{on} \tag{21}\\ P_{s,off}=&\frac {1}{6}f_{s} V_{off-state} I_{on-state} t_{off}\tag{22}\end{align*}$$ where, $V_{off-state}$ and $I_{on-state}$ are off-state voltage and switch current when the switch becomes fully turned on, respectively [32]. Also, $f_{S}$ is the switching frequency and $t_{on}/ t_{off}$ is the length of the time delay that takes for the switch to turn completely on/ off. Thus, the overall switching loss of the circuit ($P_{SW}$ ) is calculated by (23). $$\begin{equation*} P_{sw} =\sum \limits _{j=1}^{N_{switch}} {\left ({{P_{sj,on} +P_{sj,off}} }\right)}\tag{23}\end{equation*}$$

In case of conduction loss, each switching device is modeled by a parasitic resistance and parasitic voltage source (acting against the current flow), then:

$$\begin{align*} \begin{cases} P_{con-SW} =V_{on}^{sw}.i_{av-SW} +R_{on}^{sw}.i_{rms-SW}^{2} \\ P_{con-D} =V_{on}^{D}.i_{av-D} +R_{on}^{D}.i_{rms-D}^{2} \\ \end{cases}\tag{24}\end{align*}$$ where,$V_{on}^{sw}$ , $V_{on}^{D}$ are the on state voltage of switch and the on state voltage of diode, respectively. Also, $R_{on}^{sw}$ is the on-state resistance of switches and $R_{on}^{D}$ is the on-state resistance of diode [32], [33]. $\text{i}_{rms}$ and $\text{i}_{avg}$ are the RMS and average current of semiconductors. Then, the total conduction loss of the circuit is obtained by: $$\begin{equation*} P_{con}^{\,total} =\sum {(P_{con-SW} +P_{con-D})}\tag{25}\end{equation*}$$

Fig. 17 compares the efficiency of the proposed topology in various output power with similar AC-AC converters. For fair comparison, the same conditions are assumed for the converters. The parasitic resistance of the input inductor, coupled inductors, and equivalent series resistance of capacitors equal to $1~\Omega$ . Also, the ON resistances of switches are equal to $0.27~\Omega$ , and the leakage inductance of coupled inductors is $2~\mu \text{H}$ . It can be seen that from Fig. 17, the proposed converter offers higher efficiency in comparison with similar topologies. The main reasons for this reduction are a safe commutation strategy with smaller conducting duration, and input and output filter elimination which can reduce the power losses.

FIGURE 17.

Efficiency comparison.

Fig. 18 (a) and (b) show the power loss distribution of the proposed converter at an output power of 300W. It can be found that the bidirectional switches have lower power losses than other components, which proves the low conducting and switching losses of the converter. While, in the previous AC-AC converters, the significant power loss comes from semiconductors.

FIGURE 18.

Loss charts in the proposed topology at an output power of 300 W: (a) distribution and (b) circuit components losses.

SECTION VIII. Conclusion

A novel single-phase direct AC-AC converter has been presented in this paper. The proposed converter inherits all the advantages of the conventional single-phase impedance source AC-AC converters as follows: (1). It can operate in boost in-phase mode or buck-boost out of phase mode. (2). Output voltage shares the same ground with the input voltage; hence it can maintain or reverse-phase angle well with the input voltage. (3). It can be utilized as a dynamic voltage restorer to compensate voltage sags or voltage swells without using any dc storage such as battery or capacitor banks. A unique impedance network has been applied to the proposed converter to connect the ac source to the load directly. Thanks to the proposed impedance structure, it does not require passive components as input and output filters which leads to reducing in the size and cost of the converter. Magnetically coupled inductors have been employed in the proposed converter to provide high voltage boost ability with a small conducting duration of the switches by adjusting its turn ratio. As a result, the proposed converter offers high efficiency, low conducting losses and a high lifetime of semiconductors devices. A safe commutation strategy has been applied for the proposed converter to remove voltage or current spikes across the switches without needing any snubber circuits. Furthermore, the input current of the proposed converter is continuous, so it does not suffer from non-sinusoidal waveforms, high THD, high peak, and inrush current. Finally, the performance of the proposed converter has been testified within experimental results.