On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs

In this work, we demonstrate the reliability under PBTI stress of L
g
=90 nm SOI n-MOSFETS incorporating a ferroelectric-antiferroelectric (FE-AFE) 1.8 nm HfO
2
-ZrO
2
superlattice (HZH) gate stack. Notably, the HZH gate stack exhibits an equivalent oxide thickness (EOT) of 7.5 Å, 2 Å lower than the HfO
2
control, both on conventional (~8 Å) SiO
2
interlayer (IL), due to negative capacitance (NC) [1]. Considering no IL scavenging is performed, gate leakage and electron mobility of the HZH devices are not degraded. Importantly, the HZH gate stack exhibit improved PBTI reliability compared to HfO
2
. Based on a two-component model, the ΔV
T
degradation is dominated by interface trap generation as opposed to bulk electron trapping in the gate dielectric. Furthermore, the HZH gate stack displays ~20% better end-of-life (EOL) characteristics compared to HfO
2
.