Junctionless Tunnel FET for High-Temperature Applications from an Analog Design Perspective

Junctionless transistor (JLT) is known for improved short channel effects (SCE) and hence better scalability, and high temperature advantages, in addition that it offers more convenient fabrication steps. A Tunnel Field Effect Transistor (TFET) offers theoretically possible limit of subthreshold swing (SS) and has applicability for low power electronics. TFETs demonstrated in junctionless mode led to the evolution of JL-TFETs. This work analyses the performance of a JL-TFET for high temperature applications and the same is compared with a conventional p-i-n Silicon-on-Insulator Tunnel Field Effect Transistor (p-i-n SOI-TFET) at same threshold voltage. Using calibrated technology computer-aided design (TCAD) simulations, analog circuit performance parameters such as transconductance (Gm), gate-to-source capacitance (CGS), gate-to-drain capacitance (CGD), and cut-off frequency (fT) are analyzed for variation in temperature. Response to temperature is represented in terms of electrical parameters such as threshold voltage (VTH), on-off current ratio (ION/IOFF), subthreshold swing (SS). The ON-state current of the JL-TFET increases in order of hundreds of μA/μm at high temperature, whereas p-i-n SOI-TFET shows lesser temperature sensitivity.