Design and Analysis of Low-Power High Performance 4-Bit Parallel Shift Register using Retentive True Single Phase Clocked D-Flip Flop

With increase in internet enabled smart systems, circuit miniaturization and low-operating power levels are given much priority in designing next-generation integrated circuits. Shift registers are commonly used electronic devices for data storage and transmission. The performance of a shift register depends on its internal circuitry that include type of technological node, design architecture and operating power levels. The present study focuses on the design and development of 4-bit parallel in parallel out (PIPO) shift register using retentive true single phase clocked (TSPC) D flip-flop. The manuscript initially demonstrates the performance of retentive true single phase clocked D flip-flop, that makes up the proposed 4-bit PIPO shift register using 16nm technological node yielding a minimum power consumption level 0.75μW at an operational voltage of 0.8V. The power consumption of the individual TSPC D flip-flop is analyzed by varying operating voltages from 0.7V to 1.2V and its results are presented. Lastly, the 4-bit PIPO shift register is designed using TSPC flip-flop and its operation and performance is discussed. The designed 4-bit PIPO shift register can be operated below 1V operating voltage to yield minimal power consumption of around 2μW. The proposed 4-bit PIPO shift register can be possibly implemented in low power energy-efficient data handling electronic devices, which has the true potential to match current industry needs.