Optimized design of OPA in focal plane array readout circuits

This paper describes the optimized design of two kinds of operational amplifier (OPA) in the column readout circuit and output buffer of focal plane array (FPA) circuit, based on 1.2 /spl mu/m double poly double metal (DPDM) CMOS process. Hspice simulation shows that the OPA for column readout circuit works with GBW of 0.9 MHz, power of 35 /spl mu/W, settling time of 3 /spl mu/s. The OPA in output buffer can work at GBW of 12 MHz, power of 1.8 mW, settling time of 144 ns, which may support the dimension of FPA as large as 400*400 pixels at 30 frames/sec.