Multi-clock driven system: a novel VLSI architecture

This paper presents an asynchronous solution for VLSI system design. A Clock Generator, which generates a series of clock signals to drive all parts of the whole system respectively, is regarded as a control center of the architecture. This kind of structure has several advantages such as low fan-out of clock signals, low power dissipation, and flexibility for different delay times. An application of this architecture is also presented in this paper.