A novel FPGA implementation of SDH Equipment Clock

A novel cost-effective approach of SDH Equipment Clock (SEC) implementation is proposed in this paper. Based on FPGA and digital signal processing (DSP) algorithms as well as the theory of quantization and synthesis theory of digital phase processing, this approach brings lower noise generation, lower intrinsic output jitter, higher jitter transfer performance, excellent phase continuality as well as great flexibility. System diagram is given in the paper. Several distinct features are also discussed. Simulation and measurement results of such SEC implementation have demonstrated the feasibility of this approach.