A 13-Bit High Speed Two-Step Single Slope ADC Design Method for Hundreds of Mpxiel CMOS Image Sensors

This paper proposes a 13-bit fully parallel two-step single slope (TS-SS)ADC for high speed CMOS image sensors. The ADC design method is based on the idea of time sharing and time compression, advances the fine conversion time to the coarse conversion time period, and solves the time redundancy problem of the traditional method. Based on the 55nm1P4M CMOS process, the differential nonlinearity (DNL) and the integral nonlinearity (INL) are simulated to be =0.8/−0.8 LSB and +2.1/−3.5LSB, respectively. The Conversion time of the 13-bit ADC is 512 ns. The effective number of bits (ENOB) is 11.33 bits and the power consumption is $47 \mu$ W.