Board-level Solder Joint Reliability of QFN Packages with Enclosure and Placement Effects in Various Form Factors

The low cost, high performance and large capacity of Solid-State Drive (SSD) has been driving the continued growth of component density, complexity, and power consumption of these components on limited space of Printed Circuit Board (PCB). Quad flat non-lead (QFN) packages gained popularity, especially in Power Management Integrated Circuit (PMIC) device due to its low cost, compact size, and excellent thermal performance. However, board-level solder joint reliability during temperature cycling test on SSD is a critical issue not only for BGA component but also for high power QFN packages. The large coefficient of thermal expansion (CTE) mismatch between internal structures used in QFN and PCB makes the solder joint fracture during the Accelerated Thermal Cycling (ATC) condition. Thus, there is need for understanding the performance and behavior of drive into system level, as there will be another CTE mismatch in between PCB assembly and enclosure and may lead to earlier solder joint failure. In this paper we investigate and correlate the reliability of solder joints in SSD designs with multiple QFN configurations by using Finite Element Analysis (FEA). In the first section, the failure modes of QFN are evaluated. Accumulated plastic work per cycle in the solder joints arrays of multiple QFN configurations are analyzed. The simulation results are used to interpret and compare with real-life test results. Secondly, the effects of enclosure and fixation screws loading are evaluated. The results are used to study the effects of enclosure: with and without enclosure together with fixation screws loadings. The effect of QFN placements is discussed and compared with real-life test results. Lastly, the effect of form factors (U.3 Single, U.3 Bifold and EDSFF) are evaluated using the same QFN configurations and ATC where three PCB thicknesses and board dimension are tested. From the simulation results, it was found that the failure mode and location among QFN package match well with experimental results. Overall, we see that drive (with enclosure) leads to earlier failure of the system than without enclosure. The failure location is different with the enclosure and fixation screws. Accumulated plastic work per cycle in the solder joints arrays of QFN near the fixation screws was higher than other locations, which can be a dominant effect on the lifetime deterioration of the SSD performance. Furthermore, EDSFF showing stringent performance among three form factors with same ATC. In addition, optimized QFN placement with guideline on the fatigue life and fracture mode of the solder joint are discussed. This work provides realistic assessment of board-level solder joint reliability in the next generation SSD application.