Reference Clock Assessment Techniques for PCIe Gen5 and Beyond

Channel loss, crosstalk, power noise, reflections and phase-locked loop design can lead to significant degradation of high-speed signal reference clocks. This paper describes a methodology to ensure that the stringent reference clock jitter and phase noise specifications for PCIe Gen5 and subsequent standards are met for a system reference clock that crosses one or more printed circuit boards. The authors investigate real time oscilloscope and phase noise analyzer analysis methods utilizing reference designs, evaluation test vehicles, and custom clock hardware. The methods described investigate both time and frequency domain assessment, their respective advantages and disadvantages, and the precautions the signal integrity engineer must be aware of when utilizing each method to verify reference clock stability. The impact of reference clock architecture and spread spectrum clocking on the margin of PCIe Gen5 systems is important to characterize, and the test vehicles designed for this paper will characterize this important detail as future work. Finally, the analysis presented in this paper includes examples of specialized measurement techniques including use of linear amplifiers, cross-correlation and baluns combined with and without twin-axial passive probes.