Chiplet-based System PSI Optimization for 2.5D/3D Advanced Packaging Implementation

In this work, we propose a novel chiplet platform for 2.5D/3D IC Integration. Given specific design requirements, the Samsung chipletadvanced platform engine (SCAPE) can provide an integrated image of suitable advanced packaging solutionsfrom multi-chip module (MCM) or 2.5D silicon interposer or 3D stacked structures, taking into account the evaluation metrics (performance, power and area: PPA) of system and die-to-die (D2D) interconnect. It can also project an optimal design balance between system performance and cost which is closely related to die size. In a chiplet design perspective, multiple solutions for various specifications may be presented simply, but the architecture-based optimal integrated solution can be allowed only right after performance and cost are thoroughly understood. For that purpose, reference architectures are proposed to be analyzed in terms of power, area and latency at the same bandwidth requirement. As the MCM, 2.5D and 3D structures in sequence shorten the D2D distance, it can mitigate the design overhead for chiplet implementation by reducing the interface IP area and required power consumption. In terms of power and area overhead when compared to a 2D monolithic design, for homogeneously split dies, MCM, 2.5D and 3D design cases show that additional power increase 2.1%, 1.1% and 0.04% respectively and show that additional area increase by 5.6%, 2.4% and 2.4% in a HPC/AI case with 450mm² diesize. In addition, two best heterogeneous practices are created and analyzed. From the experiments, it clearly shows that 3D face-to-face (F2F) structure is the best option with obvious metrics including system power overhead of 0.11% and system area overhead of 1.9% increase for a bandwidth-centric system with 340W and 700mm²like GPU/NPU from MCM, 2.5D and 3D package candidates. Moreover, in the other latency-centric system with150W and 420mm² like CPU, it can be seen that 3D F2F case with 25μm μ-bump pitchworks up to 12.5X TBps areal BW density and 80μm C4bump pitch also work up to 8.5X W/mm² areal power density due to their physical limitation. With respect to power and signal integrity (PSI) of interface elements under various packaging candidates, this work is helpful to understand which chiplet configuration is the best option with obvious metrics and physical limitations of advanced packages, and the need to improve interfaces such as μ-bump or C4bump especially in 3D stacked ICs. We also completed a hierarchical impact diagram of configured systems considering the overhead of interface/TSV itself, die split, test circuitry, and P&R affected by the existence of TSVs. Therefore, in considering the movement toward the era of beyond Moore's Law in the performance-/cost-driven semiconductor industry, this work is expected to serve as a future chiplet reference platform which can provide differentiating solutions for quick adoption of designs.