A Design Flow and EDA-Tool for an Automated Implementation of ASIC Configuration Interfaces

The growing complexity of integrated circuits results in an increasing importance of configuration capabilities. Due to the criticality regarding the overall tapeout success, a fail-safe and error-free implementation of the configuration interface is indispensable. This paper presents a design flow together with a developed EDA-tool to satisfy this reliability demand. Key feature is the replacement of an error-prone manual implementation by an automated generation of pre-verified HDL source code. At the same time, the implementation effort for the configuration interface is significantly reduced.