Manufacturing Variation Estimation of On Resistance in Power Semiconductors

In semiconductor industry manufacturing new devices is a very complex process, composed of hundreds of steps. To ensure a high yield, design engineers are considering certain manufacturing limits of the devices. Estimation of the yield is not a trivial process as it is influenced by multiple design parameters therefore a detailed modeling of the device and high precision simulation is required. A large amount of simulation is required for this task and performing this analysis on a family of devices results in running thousands of simulations which is a very time consuming process (e.g a single finite element simulation may take tens of minutes). In this paper we propose a yield estimation method based on 3D finite element simulations. The proposed method consists of developing a prediction meta model, which has as inputs the design properties (geometry and material) of a power transistor and estimates On-State Resistance (Ron) of the device. Therefore, with just an initial number of 3D simulation, required for meta model fitting, one can predict Ron yield for an entire family of products in a matter of minutes because running any further simulations is no longer necessary. Our experiments show that we can develop accurate meta models (accuracy >99.8%) with as low as 1300 simulations. Furthermore, this meta model can be used to achieve an optimum parametric yield.