Characterization and analysis of BTI and HCI effects in CMOS current mirrors

This paper presents experimental results on the aging-induced degradation of CMOS current mirrors fabricated in a 65-nm CMOS technology. A dedicated integrated circuit array with custom test structures allowing for accelerated aging tests is used for the characterization, including several geometries of simple current mirrors, in PMOS and NMOS versions. The bi-directional link between device degradation and bias conditions that comes into play during circuit aging, as well as the permanent degradation, are both reported and analyzed.