n channel SOI Schottky barrier tunneling transistors

n channel Schottky barrier tunneling-effect transistor on SOI substrate is simulated by ensemble MC program combined with the consistent solution of Poisson's equation and Schrodinger's equation. The n channel SOI SBTT with 100 nm channel lengths is fabricated by typical CMOS technology. The gate pattern is developed by image transfer of an edge-defined spacer. CoSi/sub 2/ is used for S/D regions directly with out S/D implantation. The I-V characteristic is measured and compared to the simulation results.