DCIV diagnosis for submicron MOS transistor design, process, reliability and manufacturing

When the MOS transistor is biased in the lateral or vertical bipolar-junction-transistor configurations, a component of its DC base-terminal current originates from electron-hole recombination at the gate-conductor-covered insulator/silicon interface traps. This base-current component can be varied by the gate-basewell DC applied voltage and it peaks at a gate voltage when the electron and hole surface concentrations are about equal. The peak magnitude of the base-current, the gate voltage at the peak, and the base-current-vs-gate-voltage lineshape can reveal the spatial variations of the surface dopant-impurity and interface-trap concentrations in the five regions between the source and drain junctions (the drain and source extension and junction space-charge regions and the basewell-channel region). The sensitivity is greatly increased, as much as 10/sup 6/, by increasing the forward-bias voltage applied to one of the three p-n junctions (drain, source and basewell) of the MOS transistor structure. The device physics of this DCIV methodology are reviewed. Diagnostic applications are described for device design, fabrication process, operation reliability, manufacturing uniformity, and detection of microscopic random fluctuations from fewer impurity atoms.