Ensuring Quality of High-Speed IO Interfaces through System Level Test

In new process nodes, high-speed IO interfaces marginality caused by analog defects are resulting in a noticeable increase in customer detectable defects per million. Performance variation and signal integrity degradation become greater as high-speed IO data rates increases. In addition, printed circuit board manufacturing and environmental variances can cause increase in channel loss, cross talk, and channel discontinuities which result in increased system noise, deteriorated jitter performance and signal eye closure. The lane margining feature can help system designers assess their design's performance variation tolerance early in the design and production cycle by obtaining margin information. The same feature can be used in production Test. This paper describes new methodology used on few products to screen for marginal IO defects using System Level Test (SLT) platform.