Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm

Physically unclonable functions (PUFs) are hardware security primitives which can be used for hardware authentication and cryptographic key generation. The design of PUFs involves configuring the design of existing cells within an integrated circuit (IC) for PUF operation without impacting the normal circuit operation. This makes the design of PUF circuit very challenging especially for analog circuits as they have higher number of design specifications to meet. Thus, the design of PUFs has been explored mainly for digital circuits even though analog ICs are one of the most highly counterfeited circuit types. In this paper, we present a clear and straightforward design methodology that includes automated frequency-based analysis and evolutionary algorithm-based optimization to design a robust and reliable PUF circuit suitable for both analog and digital circuits. Specifically, we present the design of null conventional logic gate based (NCL) PUF that exploits its startup characteristics as a source of entropy. Our previous work explored a delay matching based optimization for transistors of the NCL PUF which was able to obtain a highly unique PUF with fair reliability. In this work, we are able to obtain a more robust PUF circuit with higher reliability across a wide range of temperature (0°C-120°C) and supply voltage variations (of up to ±10%). We also compare different evolutionary algorithm based techniques to demonstrate the effectiveness of our proposed methodology.