An Approach to Designing Heterogeneous Networks for High Performance Computing Systems Based on a Unified Reconfigurable Router Core

In many modern networks for High Performance Computing (HPC) systems, individual subnetworks (segments) are implemented on the basis of local area networks (LAN), other parts are implemented as networks on a chip (NoC). These types of networks use data transmission protocols that differ very significantly in their characteristics. The quality of the data transmission service (QoS) is maintained in them using various mechanisms that provide different functionality. As a result, in such heterogeneous networks it is difficult to ensure the independence of the transmission of a large number of data streams (flows), the required characteristics of the quality of service for these streams. This becomes a serious problem when organizing distributed data processing using Message Passing Interface (MPI), which is currently the de facto standard in this area. Due to the unpredictability of the data transmission characteristics, the time for tasks executing in the system also becomes difficult to predict, which in many cases is a serious problem or not acceptable at all. Another problem for HPC systems is the large amount of traffic that is transferred when performing multicast MPI operations. It can lead to local network congestion, a significant increase in the time for solving problems. In this paper, we propose an approach to designing heterogeneous networks for HPC systems based on a unified reconfigurable router core. This approach allows to eliminate the heterogeneity of characteristics in different network segments (subnetworks), to ensure a guaranteed QoS. Dynamic reconfiguration capabilities make it possible to adapt network characteristics to the characteristics of transmitted data streams, reduce the amount of transmitted data, and reduce the load on terminal nodes by performing MPI functions. This is achieved due to the use of processor cores with RISC V architecture and reconfigurable automata.