Low-Power Design of Digital LDO With Nonlinear Symmetric Frequency Generation

This brief proposes a digital LDO (Low DropOut regulator) with a built-in non-linear VCO (Voltage Controlled Oscillator) to achieve both the fast transient response and low power operation. This on-chip VCO generates a clock signal whose frequency is a non-linear symmetric function of the output voltage error. Here, we propose a design technique to realize the symmetric frequency generation with low power consumption. We demonstrate a design example of LDO using our proposed technique in a commercial 65 nm low-power CMOS process. We evaluate the LDO using transistor-level simulation using HSPICE. It achieves 0.03-
$11 ~\mu \text{A}$
of quiescent current with an input voltage range of 0.6-1.2 V and an average current efficiency of 99.68% across
$50\times $
load range.