Single Event Upset and Single Event Transient Detection in FPGA-based Search and Rescue Systems

This paper addresses the issue of obstacle avoidance in quadcopters used in Search and Rescue missions. If the quadcopter's controller is housed in a Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA), it will be susceptible to Single Event Upsets (SEUs) and Single Event Transients (SETs). It is possible to train a machine learning-based obstacle avoidance module to be inherently fault-tolerant. However, if its last stage is a comparator, errors within this comparator will not be detected. Hence, several architectures are suggested to mitigate the aforementioned errors within such a stage. They are then compared from the points of view of error detection, fault security, reliability, area, performance and power specs. These architectures are also compared to already existing techniques in terms of most of the previously stated specs after implementing them on Altera Cyclone IV E EP4CE22F17C6 FPGA. It is important to note here that the goal of this paper is not to find the best solution to SEUs and SETs but to suggest several solutions, where a solution can be superior to others according to the situation, i.e., application appropriateness is left to the user.