Low Power Carry Select Adder using FinFET Technology

This paper presents an idea for designing carry select adder using 16nm FinFET technology. Adders plays a pivotal role in the arithmetic operation as well as in address calculation, which is used for different applications. In addition to this, adder is also one of the fundamental circuit used in portable electronic systems such as laptops, smart gadgets etc. As we know that, for these portable devices, consumption of power should be less for longer battery life. Therefore, reducing power consumption is one of the utmost requirement. Considering various adder topologies, it is seen that CSA is widely used circuit for the electronic devices. Hence, reduction of power consumption of 4-bit CSA is achieved in the present work by using hybrid full adder cell consisting of 22 transistors. Three different design topologies viz. Design-I, Design-II and Design-III for designing CSA is discussed and compared for various parameters such as power, delay and PDP. Simulations are done using Synopsys HSPICE tool with a supply voltage of 0. 8V and PTM-MG 16nm technology. The power consumption calculated for the proposed work is 4.98E-07 watt for design-I, 4.91E-07 watt for design-II and 3.57E-07 watt for design-III respectively.