Review of FPGA-Based Accelerators of Deep Convolutional Neural Networks

Recent research has shown that Deep Convolutional Neural Networks (CNNs) are extremely accurate in a big range of cognitive tasks. This has piqued the interest of researchers. FPGAs are regarded as an attractive platform for hardware acceleration of CNNs due to their performance, flexibility, and energy efficiency. To improve the performance of CNNs, numerous accelerators have been employed, including ASICs, FPGAs, and graphics processors (GPUs). The use of FPGAs to accelerate deep learning networks is primarily driven by their high power efficiency and their ability to maximize parallelism. To provide comparisons and differences regarding the various techniques used to implement and optimize CNN algorithms on FPGA, the works were categorized into categories. Recent advances in deep learning networks using FPGA-based accelerators are described in this paper. This review should guide future advances in hardware acceleration and make deep learning research more efficient.