Simulation of Optimum Stored Charge in SONOS FLASH Memory using Silvaco TCAD

The simulation of several SONOS memory cells in SILVACO TCAD is presented in this work. By adjusting the nitride layer thickness from 4 to 6 nm and keeping the gate voltage constant at 16 V, the effect of multiple nitride layer and tunnel oxide layer thicknesses on the charge distribution in the floating nitride gate is investigated in net stored charge. As the nitride layer changes, The I-V curve shows the shifting of the threshold voltage. In the floating gate, the spatial distribution of trapped electrons is detected, which varies when the thickness of the nitride layer is adjusted. The nitride layer thickness of 6 nm shows 17% of net charge variation for logic 0 states with $4^{\mathrm{t}\mathrm{h}}$ order of transition time window and maximum $4.6\times 10^{-15}$C of the net charge stored. By altering the tunnel oxide layer thickness from 1.5 to 3 nm while keeping the nitride layer constant at 4 to 6 nm, it found a decrease in net stored charge. The I-V curve illustrates threshold voltage shifts as the tunnel layer thickness varies. Furthermore, it was discovered that tunnel oxide layer thickness of 2 nm offers net charge variation for logic 0 states with $3^{\mathrm{r}\mathrm{d}}$ order of transition time window and max $4.7\times 10^{-15}\mathrm{C}$ of the net charge stored. In contrast, the thickness of 1.5 nm offers 57% of net charge variation for logic 0 states with $2^{\mathrm{n}\mathrm{d}}$ order of transition time window and max $4.4\times 10^{-15}\mathrm{C}$ of the net charge stored. The optimized thickness layer of both nitride and tunnel oxide model of SONOS is presented with electron concentration profiles at logic 1 and logic 0.