An Efficient VLSI design of Median Filters using 8-bit Data Comparators in Image Applications

In image applications, noise removal is one of the important requirement. Impulse noise is removed by median filters using image processing. Median filter is the good non-linear filter used for edge preservation in images and in real-time hardware implementation, sorting network is used. Sorting network must have an efficient implementation in terms of area, delay and power. Row three cell sorter, column three cell sorter, and right diagonal three cell sorter comprise the median filter. The median value of the inputs is the output of the median filter. Three data comparators give the maximum, minimum and middle value in the three cell sorter. The comparator returns the highest and lowest value of given inputs. The middle value is calculated using a modified shear sorting method. This paper compares two existing data comparators and suggests a modified version of those two existing comparators in factors of delay and area. Full adders and full subtractors are used to build the proposed comparators using MUX. The two’s complement based data comparator consumes less time. As a result, an implementation using two’s complement is suited for high-speed implementations. The carry select data comparator based implementation consumes smaller area, hence it can be employed in reduced area applications. The median filter is intended to be used with a two’s complement based data comparator. In the parallel architecture of modified shear sorting for constructing median filter, different architectures for data comparators were used.