Measurement of Circuit Parasitics of SiC MOSFET in a Half-Bridge Configuration

Fast switching transient of SiC
mosfet
reduces switching loss. However, it excites device and circuit parasitics resulting in prolonged oscillation, high device stress, spurious turn
on
, EMI related issues, and higher switching loss. Behavioral or analytical models are used to estimate switching loss
$(dv/dt)$
,
$(di/dt)$
rates, etc., and it requires the value of circuit parasitics as input. Measurement is the only way to accurately estimate some device package-dependent circuit parasitics when the internal package geometry is unknown. Hence, measurement of circuit parasitic is essential for optimal design. This article presents a set of simple experimental measurement techniques to determine circuit parasitic inductance and capacitances relevant for switching transient study of SiC
mosfet
in a half-bridge configuration. The accuracy of the proposed technique is verified through simulation and experimental results of the hard turn
off
and capacitor assisted soft turn-
off
dynamics of SiC
mosfet
over a range of operating conditions for two 1.2-kV discrete SiC
mosfet
of different current ratings and two different PCB layouts. Furthermore, the proposed technique is also validated with the existing frequency response analysis-based impedance measurement.