Multi-Sampling With Real-Time Update PWM for Time-Delay Minimization of FPGA-Based Voltage-Controlled Converters

Time delay usually limits control bandwidth and deteriorates the stability of digital control system. This paper presents the mechanism and optimization of the multi-sampling with real-time update PWM method for time-delay minimization. The relationship between modulation-wave update latency and digital delay is firstly analyzed by the graphical illustration, revealing that desired implementation of equivalently eliminating computation delay will be limited by large update latency. Further, to minimize update latency, the FPGA is employed to realize the resonant controller based voltage control, thanks to its advantage of fast-paralleled calculation. Compared with traditional multi-sampling with multi-update PWM, the presented method further reduces the digital delay by up to 66%. Its effectiveness is validated by the platform of a single-loop voltage-controlled converter with an inductor (
$L$
)-filter.