An Insightful Assessment of 1T-DRAM With Misaligned Polarity Gate in RFET

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin
$\ge 6~\mu \text{A}/\mu \text{m}$
, retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~10
⁴
along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented.