Rehosting YOLOv2 Framework for Reconfigurable Fabric-based Acceleration

While Convolutional Neural Networks are attaining widespread utility for computer vision tasks such as object detection and classification, the frameworks used to implement these systems are largely designed for use with CPUs and GPUs, with the latter being the hardware-optimized approach. This application-optimized hardware approach can be advanced further by researching Convolutional Neural Networks implemented on low-power and embedded devices using FPGAs. FPGAs consume substantially less energy than GPUs, offering additional potential benefits for embedded hardware acceleration of Convolutional Neural Nets. Because GPUs are still the favored target device for CNNs, there is an abundance of libraries and tools that can be used to create custom architectures in languages such as Python and C++. This, however, is not the case for FPGA development. Herein, a workflow is outlined for the conversion of Convolutional Neural Networks from a high-level language implementation to a bitstream which can be configured on an FPGA device and utilized as a hardware accelerator for image and video processing. Within this workflow, the data is quantized to reduce memory usage, C++ code is synthesized to Verilog using Vivado HLS tools, the resulting hardware module is integrated with the ZYNQ SOC processor, and the final implementation is tested for accuracy.