Implementation of Barrel Shifter in Vedic Multiplier

This paper is about designing 16-bit (VM) Vedic multiplier using barrel shifter boosted in-charge of the delay when it is compared with the conventional multipliers such as the modified booth multiplier, the array multiplier, the Wallace tree multiplier and the Braun multiplier. In this VM design, the barrel shifter is used, which only needs a clock cycle for the entire shifts. This Vedic multiplier (VM) design is verified by using Tanner EDA software. The delay and power consumption are also verified by using T-spice in Tanner software. The delay achieved by this design is 5.8ns using barrel shifter in multiplier.