Heterogeneous Integration of Chiplets: Cost and Yield Tradeoff Analysis

With the decline of Moore’s law, it has become incumbent on organizations to change the way large and complex chips are architected. As SoC sizes hit reticle limits, fabricating this die coupled with the poor yield of large die at cutting edge process nodes makes it cost prohibitive. Heterogeneous integration of chiplets optimized at different process nodes becomes a very practical alternative. This chiplet style of integration also lends itself to greater IP reuse and a faster time to market.For organizations to determine if a specific SoC should be fabricated as a monolithic vs. a disaggregated system, there needs to be the ability to model the cost and tradeoffs and then build a business case. The work done here provides this ability – it provides the user with an open-source model into which he/she can feed in proprietary data to model the SoC as multi chiplet integrations at various optimized process nodes, with active and passive devices. The output of the model provides details of the cost – material, test, KGD, operations etc. for both a monolithic version of the SoC as well as a system of chiplets. It enables the user to get a 1^st pass look at the largest contributors to the cost and if disaggregating the SoC makes a good business case.