Data Acquisition System Based on FPGA/SOPC

A field-programmable logic gate array (FPGA) based data acceleration acquisition system is designed. A 100MHz clock signal is generated using a phase-locked loop, which is applied to the synchronous dynamic random memory (SDRAM) to make it work properly. A 100Hz sinusoidal signal is sent internally by the FPGA, which is stored in the SDRAM and sent to the host computer for display.