The Acceleration Techniques for the Modified Pathfinder Routing Algorithm on an Island-Style FPGA

The paper presents two techniques to speed up routing of user circuits within an island-style FPGA design flow. The basic algorithm is the modified Pathfinder that supports a mixed route graph representation of FPGA routing resources. The first technique reduces the number of rip-up and reroute iterations and allows decreasing routing time by 38% on average while increasing the critical path delay up to 10% only. The second technique utilizes the idea of directed pathfinding on a mixed route graph with known geometric coordinates of its vertices and edges. Various values of directed path search adjustment factor were investigated and the optimal one was discovered. The introduced routing method adjusted by an optimal factor value is shown to double a routing speedup without routability degradation. Also, the paper proposes a formal description of FPGA routing resources and a routing task itself.