A Detailed Power Analysis of Network-on-Chip

In a multi-core general purpose processor or System-on-Chip, interconnection network plays a very important role. An on-chip interconnection network or Network-on-Chip may be designed to achieve maximum throughput or minimum latency depending on the type of application to be run on the processor. In this paper we present an analysis of effect of different parameters like network size, routing, traffic patterns, flit size, buffer size on power consumption of the Network-on-Chip. We also discuss the trade-offs between power, throughput, and delay metrics for an efficient network operation. Our analysis will help in designing new routing algorithms, allocation algorithms for Network-on-Chip.