Dead-Time Compensation in Active NPC Three-Level Inverters Considering Current Ripple

Existence of dead time that makes the ultimate terminal voltage being inconsistent with the modulation voltage, is recognized as the main reason for leading output voltage distortion, as well as the corresponding low-frequency current harmonics through the filter inductance in inverters. The distortion becomes particularly severe in high power-density high efficiency applications where the wide bandgap semiconductors are gradually being adopted, providing higher switching frequency with small junction capacitance. In order to explain this phenomenon, the mechanism of three-phase current distortion in the vicinity of phase current zero-crossing point is thoroughly studied by vector analysis in the space-vector (SV) plane. The relevant factors that lead to the degradation of current quality are also summarized. Improved compensation strategy has been proposed to ameliorate the current distortion. Compared with the conventional method, an additional item for current ripple compensation is introduced, the value of which is obtained by the deadbeat predictive method. This simple scheme avoids the compensation error caused by current ripple and significantly reduces the current total harmonic distortion (THD) value under the case of small inductance. Furthermore, neutral-point (NP) potential balance control is also considered in conjunction with the scheme. Simulations and experiments are carried out in an active NP clamped (ANPC) inverter platform, which demonstrates the validity of theoretical analysis and the proposed method.