A Proposal for Design and Implementation of a Low Power Test Pattern Generator for BIST Applications

With the increasing demand of embedding more functions in VLSI chips, it has become vital for the engineers to come up with a solution that necessitates battery durability and minimizes power dissipation along with appliance weight. Dynamic power dissipation is the result of logic alterations (switching) that charge and discharge the load capacitances in transistors. In DFT systems, when a circuit operates in normal mode, the successive vectors applied have a considerable concurrence among them. In case of LFSRs as TPGs in a BIST environment, this correlation between consecutive vectors is low. This will lead to a consequential elevation in switching actions within the circuit which can make the test power as high as two times of that in the typical operating mode. Hence, reducing power utilization throughout test has turned into a major goal in modern VLSI systems. This paper presents a low power LFSR which is designed and simulated using two clock gating concepts and then a comparison is done between them. Their RTL schematic, simulation results and reports of power analysis are shown. The tool used for circuit implementation and analysis is Xilinx Vivado.