FPGA Implementation of Time-Interleaved Pruning Neural Network Equalizer for Short Reach Optical Interconnects

A time-interleaved parallel pruning neural-network equalizer is proposed and implemented on FPGA for 100-Gbps PAM-4 optical interconnects, demonstrating over 55% and 40% hardware resource reduction for single and 8-channel equalization. © 2021 The Author(s)