Optimizing the Page Hotness Measurement with Re-Fault Latency for Tiered Memory Systems

Constructing tiered memory systems becomes prevalent in cloud and datacenter servers due to its benefits on large capacity and low total cost of ownership. Since such tiered memory systems usually comprise low-latency memory (e.g., DRAM) and high-capacity but high-latency memory (e.g., Nonvolatile memory), accurately measuring the page hotness is one of the most important factors. This paper uncovers the inefficiency of the short-term page hotness measurement proposed by recent work and explores how to detect short-term page hotness more precisely. Our proposed scheme tracks successive page accesses through recursive TLB misses and calculates the latency, called re-fault latency. Page migration decision is performed based on this re-fault latency. We evaluate our scheme on real hardware consisting of DRAM and Optane DC PMM and confirm that the proposed scheme outperforms the recent work by up to 1.51x.