Loading web-font TeX/Math/Italic
Analysis and Design of High-Efficiency Charge Pumps With Improved Current Driving Capability Using Gate Voltage Boosting Technique | IEEE Journals & Magazine | IEEE Xplore

Analysis and Design of High-Efficiency Charge Pumps With Improved Current Driving Capability Using Gate Voltage Boosting Technique


Abstract:

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an inpu...Show More

Abstract:

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- \mu \text{m} standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved \sim 1.24\times more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%.
Page(s): 2364 - 2375
Date of Publication: 15 March 2022

ISSN Information:

Funding Agency:


References

References is not available for this document.