A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch

Comparators are the core of analog-to-digital converters (ADC), used as sense amplifiers in on-chip data-communication links and memories. The time taken by a clocked comparator to resolve analog inputs near its input-referred noise level into digital output (called CLK-OUT delay, Fig. 3.3.1) often dictates the system's throughput for a given SNR. For SAR ADCs where each bit is determined sequentially, CLK-OUT delay presents a bottleneck in realizing high-speed operation, e.g. beyond 1 00MS/s in 5G/6G baseband application. For a 12-bit 100MS/s SAR ADC at 1 V, e.g., the comparator should resolve signals below 0.5mV within 500ps. Time-interleaving increases ADC throughput but at the cost of increased clock power. Therefore, low-noise energy-efficient GS/s comparators with sub-500ps CLK-OUT delay are indispensable not only for multi-Gb/s serial communication, but also in 5G/6G baseband ADCs. By eliminating static current, dynamic comparators (e.g. Elzakker [1], dynamic bias [2], inverter-amplifier [3]) perform comparisons with high energy efficiency for a given noise level. However, the energy-efficiency of these techniques [1]–[3] has been demonstrated only at low comparator speeds (below 100MS/s) with CLK-OUT delay in the range of a few ns [2] to tens of ns [3]. High-speed (GS/s) comparators [4]–[7] have been demonstrated at only medium noise level (a few $\text{mV}_{\text{RMS}}$) and are energy-inefficient. This work presents an energy-efficient GS/s comparator targeting low-power and low-noise applications in high-speed ADCs and serial communication. The proposed comparator's CLK-OUT delay and input-referred noise remain well within 500ps and $0.5\text{mV}_{\text{RMS}}$ over wide input-common-mode voltage, $\mathrm{V}_{\text{CM}}$ (0.3 to 0.6V) while still maintaining <100fJ per comparison.