Design and Verification of Three-stage Pipeline CPU Based on RISC-V Architecture

RISC-V is a new open-source instruction set architecture, which has received extensive attention from the industry, and it is explored and designed in this context. Based on the RISC-V instruction set architecture, this paper designs a processor that supports a subset of the RV32IM instruction. It uses a three-stage pipeline technology, namely, value, decoding, and execution modules, with static branch prediction and Harvard storage structure. The main modules are pipeline module, control module, interrupt exception and storage module. Iverilog was used for simulation testing and passed the RISC-V test case. The final result showed that the processor can run normally at a clock frequency of 50MHz.