The comparator design research

Four innovative designs and improved designs of the comparators are studied in this work. The floating inverter amplifier (FIA)-based preamplifier design is used in the comparator to improve energy efficiency. A latch-type comparator with a dynamic bias preamplifier ensures low energy consumption. An innovative comparator, the edge-pursuit comparator (EPC) comparator, uses NAND gates and inverter delay cells to allow two input signals to chase each other. Its structure makes it have some important features for the comparator, such as input noise tunability, automatic energy scaling and low voltage tolerance. Still, it also suffers from the offset voltage. A triple-latch feedforward (TLFF) dynamic comparator consists of three stage latches and a parallel feedforward path, optimising the delay, especially for large signals. However, the power consumption of the comparator is higher than other comparators. The performances of these comparators are compared in this paper.