Design of Combinational Logic Circuits using Simulated Annealing

Conventional methods to design combinational logic circuits (CLCs) is time consuming and needs expert knowledge. Evolutionary computing techniques have proved to be a competitive field for the evolution of CLCs. Simulated annealing is a metaheuristic which helps in finding a global optimum for a given function. The proposed work aims to design CLCs using simulated annealing (SA). Various circuits proposed in the literature are realized and experiments reveal that a maximum of 33.33% of resources are saved and 2.0x speed enhancement is achieved over the circuits reported in literature. The proposed work acquires the design requirements from the designer/user to yield scripts for FPGA implementation.