An FPGA-based Piecewise Linear Spiking Neuron for Simulating Bursting Behavior

Modeling and hardware implementation of artificial neurons is an important goal in the field of neuromorphic and brain-inspired computing. The neuronal digital circuit of the piecewise linear spiking neuron (PLSN) model is designed and implemented on a field programmable gate array, where all computation processes in the arithmetic tree are pipelined to maximize the parallelism of time and space. Based on the different properties of bursts in neuronal firing, the hardware is used to demonstrate two classes of bursting behavior of the PLSN model: forced bursting and intrinsic bursting. We also analyze the generation mechanism and bifurcation phenomenon of the intrinsic bursting and simulate a type of cortical neurons with the bursting behavior.