Simulation-Based Study of Low Minimum Operating Voltage SRAM With Inserted-Oxide FinFETs and Gate-All-Around Transistors

A six-transistor (6T) static random access memory (SRAM) cell design comprising inserted-oxide fin field-effect transistors (iFinFETs) is compared against other 6T SRAM cell designs comprising either FinFETs, gate-all-around (GAA) nanowire field-effect transistors (NWFETs), or forksheet field-effect transistors (FSHFETs). The FSHFET and iFinFET SRAM exhibit better read stability, write ability, and lower minimum operating voltage (
${V}_{\text {min}}{)}$
for the same cell size. To further reduce
${V}_{\text {min}}$
, we propose integrating high-current seven-nanowire iFinFETs with low-current three-nanowire NWFETs to achieve pull-up (PU):pass-gate (PG):pull-down (PD) ratio of 3:7:7. Due to a better PU ratio (0.41 versus 0.80),
${V}_{\text {min}}$
of 3:7:7 hybrid SRAM is reduced from 0.61 V of 7:7:7 iFinFET SRAM to 0.54 V without increasing the read or write access time. The static power consumption is reduced from 26 to 13 pW, and the dynamic power consumption is reduced from 117 to 101 nW due to lower gate capacitance and leakage current for the PU transistors.